1. Field of the Invention
The present invention relates in general to integrated circuit (IC) testers and in particular to a linear ramping digital-to-analog converter for generating test signal outputs for an IC tester.
2. Description of Related Art
An integrated circuit (IC) tester tests the logic of a digital IC by applying digital signals to its inputs and monitoring the IC's digital output signals to determine if they behave as expected. An IC tester usually includes a separate channel connected to each terminal of the IC, with each channel including a tristate driver and a data acquisition circuit. When the terminal is an input terminal, the driver sends it a square wave test signal abruptly changing between high and low logic levels at specific times during the test. When the terminal conveys an IC output signal the data acquisition circuit samples the IC output signal at various times during the test to determine whether it is of an expected logic state.
In a general purpose IC tester the driver's high and low logic levels are adjustable because the various ICs it may test have differing logic levels and because it is helpful to test an IC over a range of logic levels to determine its tolerance for variation in input logic level. Some testers use digital-to-analog converters (DACs) to produce reference voltages for controlling the driver's high and low output signal levels. A DAC produces an output voltage of magnitude proportional to the value of its digital input data, and when its input data value changes the DAC quickly steps its output voltage to a new level.
A tester employing one DAC to generate the high logic level and one DAC to generator the low logic level supplies the appropriate data to each DAC before the start of a test to set the desired high and low logic levels. The DAC output voltages are supplied to the channels' drivers for use as references when generating their output test signal. During a test the tester supplies a two-bit wide control data sequence to each driver. A "DRIVE" bit tells the driver when to switch its output signal between its high and low logic levels while the second bit (a "TRISTATE" bit) tells the driver when to tristate its output. The timing of the control data bits controls the timing of the state changes in the driver's output signal. A tester also supplies a separate data sequence to the comparator circuit for each channel to tell each comparator when to sample an IC output signal and to also indicate the expected logic state of the IC output signal.
A test is normally organized into a succession of test cycles of uniform duration. A tester typically employs one or more pattern generators for supplying a separate data word (a "vector") to each tester channel prior to the start of each test cycle. The vector indicates the test activity or activities the channel is to carry out during the test cycle and indicates times during the test cycle when the channel is to carry out those activities. A "formatter" circuit within each channel decodes the vector to produce the control data supplied to the channel's driver and data acquisition circuits during the test cycle. With regard to the driver, the vector indicates how and when during the test cycle the formatter is to change the state of the DRIVE and TRISTATE bits.
We can think of the pattern generator, the formatter, the driver and the level control DACs within each channel as forming a waveform generator producing a square wave output signal having levels controlled by the DACs and having edge timing controlled by the vector data sequence produced by the pattern generator. This waveform generator has a limited flexibility in producing an output waveform because while it can flexibly adjust timing of square wave edges, it can only set the square wave between the two discrete levels defined by its reference DAC outputs. In order to drive the test signal to other levels, the tester has to stop the test, supply new data to the DACs, and then restart the test.
It would be beneficial if the waveform generator were capable of providing a wider range of waveforms as test signal inputs to an IC. For example, to test an IC to determine its tolerance for noise in an input signal we would like to add high frequency simulated noise components of desired magnitudes to the square wave test signal. A conventional digital tester can't do that because its test signal output is limited to two levels.
Analog IC testers use an arbitrary waveform generator (AWG) to produce a waveform having any of a large number of magnitude levels. A simple arbitrary waveform generator includes a pattern generator supplying a data sequence as input to a DAC. By adjusting the nature and frequency of the data sequence supplied to the DAC we can make the DAC produce a "stepped" approximation of essentially any analog waveform we like within the resolution, range and frequency limitations of the DAC. The AWG output waveform is not smooth because the DAC can only produce discrete voltage levels, but if we increase the resolution of the DAC and the frequency with which we update its input data, its output signal voltage steps become smaller, and its output signal begins to more closely approximate a smoothly varying analog signal. However since high resolution, high frequency DACs are expensive, and since high frequency operation requires a pattern generator to produce a very long waveform data sequence at a high rate, there are practical limits to how close we can make a conventional, stepped AWG output signal approximate a smoothly varying analog signal.
One solution to smoothing the stepped output signal of a DAC is to pass it through an analog filter. Filtering the signal removes abrupt edges and make its more closely approximate a smoothly varying analog signal. Although arbitrary waveform generators are occasionally used to supply test signal inputs to digital integrated circuits, their use in generating signals having high frequency components is problematic. Although high frequency, high resolution AWGs are expensive, perhaps the most important limitation to their use in high frequency digital IC test applications relates to their output signal filters. An IC tester has to precisely time a test signal, but when we pass an AWG output signal through a filter, the filter time skews various frequency components by differing amounts and therefore distorts the signal. We can compensate for that distortion to some extent by the way we program the pattern generator, but that is difficult to do. Also an AWG's output filter may have to be appropriately tuned to account for the desired frequency characteristics of the waveform the AWG produces. This means that a tester employing a conventional AWG would have to include a complicated tunable filter for each channel, and that filter may have to be retuned whenever the nature of the waveform it is to produce changes.
What is needed is an inexpensive, high resolution AWG for an integrated circuit tester that can produce an output waveform that closely approximates a smoothly varying high frequency analog signal without being filtered.